The present invention is directed to design and verification of electronic circuits and, more particularly, to a method for verifying the design of a digital to analog converter.
Electronic design automation (EDA) tools are often used to design and verify integrated circuits (ICs), which may include many different types of modules. Hardware description languages (HDLs) are languages used to describe IC designs, their operation and their relation within the IC. A common HDL used for digital circuits is Verilog, which is standardized as IEEE 1364, and a common HDL used for analog and mixed signal (AMS) circuits are Verilog-AMS, which has an option digital-centric mixed signal verification, called the DMS option, and VHDL which is standardized as IEEE standard 1076.1-1999. Verification includes verifying the performance that will result from the IC structure and its modules and elements, and the electrical characteristics chosen for the modules and elements and their inter-relations.
A digital to analog converter (DAC) receives a digital input signal and produces an analog output signal of equivalent value. Verifying the performance of a DAC at the design stage avoids the need to synthesize the real hardware modules and elements, and to manufacture and test physical prototypes, which are laborious, expensive and time-consuming tasks and in addition leave ambiguity between design imperfections and manufacturing imperfections. Using a HDL representation of a DAC, the performance to be expected from its design can be verified using a simulator or checker, which mathematically calculates the performance characteristics to be expected from the detailed design. The simulation and the verification can then be iterated for variants of the design. However, if the simulation has to be configured to run different cases of input signal ranges, and the corresponding expected output signals in accordance with the specification have to be calculated prior to the simulation, the verification process is inconvenient and slow.